1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to a gate-in-panel (GIP) type liquid crystal display (LCD) device and a method of fabricating the same.
2. Discussion of the Related Art
As the information age progresses, display devices for displaying information are actively being developed. More particularly, flat panel display (FPD) devices that are thin, light weight, and do not consume much power are actively being pursued. Among the various types of FPD devices, liquid crystal display (LCD) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, color rendering capability and superiority in displaying moving images.
The LCD device displays images by controlling light transmittance through the device. More particularly, liquid crystal molecules interposed between two substrates that face each other, control light transmission in response to an electric field generated between respective electrodes on the two substrates.
The LCD device may include a liquid crystal panel having two substrates and a liquid crystal layer between the two substrates, a backlight unit under the liquid crystal panel and a driving circuit unit outside the liquid crystal panel. The driving circuit unit may be formed on a printed circuit board (PCB). The PCB may be classified into a gate PCB and a data PCB connected to a gate line and a data line of the liquid crystal panel, respectively. The gate PCB and the data PCB are disposed at sides of the liquid crystal panel. The gate PCB as a tape carrier package (TCP) is connected to a gate pad portion at one end of the gate line, and the data PCB as a TCP is connected to a data pad portion at one end of the data line. For example, the gate PCB and the data PCB may be disposed at a left side and a top side of the liquid crystal panel, respectively.
When the gate PCB and the data PCB are connected to the gate pad portion and the data pad portion, the LCD device is large and heavy. To reduce size and weight of the LCD device, a gate-in-panel (GIP) type LCD device including a single PCB including a driving unit has been suggested.
FIG. 1 is a schematic plane view showing a gate-in-panel type liquid crystal display device according to the related art, and FIG. 2 is a schematic cross-sectional view taken along a line “II-II” of FIG. 1. In FIGS. 1 and 2, a gate-in-panel (GIP) type liquid crystal display (LCD) device 1 includes an array substrate 10, a color filter substrate 50 and a liquid crystal layer 70 between the array substrate 10 and the color filter substrate 50. The array substrate 10 includes an active area “AA” displaying images, a pad area “PA” at an upper portion of the active area “AA,” a gate circuit area “GCA” at a side portion of the active area “AA” and a signal input area “SIA” outside of the gate circuit area “GCA.”
A gate line 13 and a data line 28 cross each other to define a pixel region “P” and are formed in the active area “AA” on the array substrate 10. A gate insulating layer 21 is interposed between the gate line 13 and the data line 28. In addition, a thin film transistor (TFT) “Tr” is connected to the gate line 13 and the data line 28, and a pixel electrode 43 in the pixel region “P” is connected to the TFT “Tr.” A data pad 46 connected to the data line 28 and a gate pad 47 connected to a first connection line 18 in the signal input area “SIA” are formed in the pad area “PA.” Even though not shown in FIG. 1, a driving circuit unit as a tape carrier package (TCP) may be connected to the pad area “PA.” A plurality of circuit blocks 48 each including switching elements and capacitors are formed in the gate circuit area “GCA.” Each circuit block 48 is connected to the gate line 13 in the active area “AA” and a plurality of second connection lines 35 in the signal input area “SIA.” As a result, a plurality of first connection lines 18 and the plurality of second connection lines 35 are formed in the signal input area “SIA.” The plurality of first connection lines 18 extend to the pad area “PA,” and the plurality of second connection lines 35 cross the plurality of first lines 18. The plurality of second connection lines 35 are connected to the plurality of circuit blocks 48 in the gate circuit area “GCA.”
A black matrix 53 for preventing light leakage is formed on the color filter substrate 50. The black matrix 53 may cover a border line of the pixel region “P” and a boundary of the color filter substrate 50. A color filter layer 58 including red, green and blue color filters 58a, 58b and 58c is formed on the black matrix 53. The color filter layer 58 corresponds to the active area “AA,” and the red, green and blue color filters 58a, 58b and 58c are alternately disposed in the pixel region “P.” A common electrode 60 of a transparent conductive material is formed on the color filter layer 58.
Since the GIP type LCD device 1 includes the single TCP (not shown) instead of two TCPs such as a gate TCP and a data TCP, the array substrate 10 includes the gate circuit area “GCA” and the signal input area “SIA” instead of a gate pad area. In addition, the plurality of first connection lines 18 in the signal input area “SIA” extend to the pad area “PA” and are connected to the gate pad 47 in the pad area “PA.” As a result, the single TCP is attached to the gate pad 47 and the data pad 46 in the pad area “PA” and external signals are input to the GIP type LCD device 1 through the gate pad 47 and the data pad 46.
The gate insulating layer 21 is interposed between the first connection lines 18 and the second connection lines 35. A passivation layer 38 is formed on the data line 28 and the plurality of second connection lines 35. The passivation layer 38 may include a first contact hole 42 exposing both the first connection lines 18 and the second connection lines 35 in the signal input area “SIA.” A gate connection pattern 44 on the passivation layer 38 contacts the first connection lines 18 and the second connection lines 35 through the first contact hole 42. The first connection lines 18 and the second connection lines 35 are electrically connected to each other through the gate connection pattern 44. As a result, a plurality of gate connection patterns 44 are formed on the passivation layer 38 in the signal input area “SIA” to contact the plurality of first connection lines 18 and the plurality of second connection lines 35.
A seal pattern 80 is formed at a boundary portion outside the active area “AA,” and the array substrate 10 and the color filter substrate 50 are attached to each other. The seal pattern 80 is formed of a sealant including a conductive ball 75 to apply a common voltage to the common electrode 60 of the color filter substrate 50. A common line (not shown) supplied with a common voltage from the driving circuit unit is formed at the boundary portion of the array substrate 10. Since the seal pattern 80 having the conductive ball 75 contacts the common line, a common voltage may be applied to the common electrode 60 of the color filter substrate 50 through the conductive ball 75. However, since the plurality of gate connection patterns 44 of the array substrate 10 and the common electrode 60 of the color filter substrate 50 are exposed to the seal pattern 80, the common electrode 60 can be electrically connected to the plurality of gate connection patterns 44 through the conductive ball 75 of the seal pattern 80. Accordingly, the common line 60 and the plurality of circuit blocks 48 can be electrically shorted, and the GIP type LCD device 1 does not operate normally.